One or more aspects relate, in general, to improving system performance within a computing environment, and in particular, to managing cache coherency within the computing environment.
A typical enterprise server computer system comprises multiple processor sockets that may be interconnected together coherently in a variety of Symmetrical Multiple Processor (SMP) bus topologies so as to achieve the overall system capacity to meet the needs of the enterprise. The larger the SMP size in the server, the higher the coherent traffic is on the SMP buses and the greater the skew is on multiprocessor intervention latencies.
Due to physical constraints in how the processors can be interconnected, most common topologies involve grouping the processors into any number of nodes where the processors within a node have the fastest communication links to one another compared to processors in other nodes. Furthermore, the same constraints may drive partitioning of the total number of nodes into smaller SMP regions or groupings.
In cases where the SMP topology consists of many processor nodes and where the cache intervention times of remote nodes can exceed local memory access times, performance improvement can be achieved by assigning much of the memory and processors needed for a task to be physically closer than the rest of the system, i.e., assigning the task to an SMP region or grouping.
Even if one hundred percent localized affinity of memory and processors to an SMP region can be achieved, one or more operations that exist in certain coherent cache states still need to make a full address broadcast and coherency response round trip on the topology in order to be serviced.